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Verify level control criteria for multi-level cell flash memories and their applications

Yongjune Kim1, Jaehong Kim2, Jun Jin Kong2, B V K Vijaya Kumar1* and Xin Li1

Author Affiliations

1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, 15213, USA

2 Samsung Electronics Co., Ltd., Gyeonggi-do, 445-701, Hwasung, Korea

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EURASIP Journal on Advances in Signal Processing 2012, 2012:196  doi:10.1186/1687-6180-2012-196

Published: 5 September 2012


In 1M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.